Insulation structures that insulate neighboring, active regions in the semiconductor substrate from one another are formed in the manufacture of integrated circuit arrangements in semiconductor substrates. What are referred to as shallow trench insulations are being increasingly employed in LSI circuits. These are thereby trenches that are filled with insulating material, usually oxide. A planarization is implemented wherein the surface of the active regions is uncovered and the surfaces of the oxide fills are maintained at approximately the same height as the surface of the active regions. The planarization in the manufacture of shallow trench insulations usually occurs with chemical-mechanical polishing.
Since the width of the insulation structures in integrated circuits is usually not constant over the entire integrated circuit, insulating trenches of different widths are formed in shallow trench insulation. Beyond this, the thickness of active regions and insulating trenches fluctuates highly. This leads to difficulties in the planarization, so that the surface that derives also exhibits steps after the planarization that are often referred to as topology steps.
In order to avoid topology steps in planarization with chemical-mechanical polishing, it has been proposed to employ an additional lacquer planarization mask (see B. Davari et al, IEDM Tech. Digest, p. 61 (1989)). After deposition of an insulating layer that is employed for filling the trenches, supporting locations of lacquer are thereby formed in wide trenches. Subsequently, a further lacquer layer is applied in surface-wide fashion, this exhibiting an essentially planar surface due to flowing. Proceeding from this planar surface, the planarization is implemented by chemical mechanical polishing until the surface of the active regions is uncovered. The supporting locations of lacquer and the further lacquer layer are thereby removed. The supporting locations of lacquer must be tempered so that the supporting locations of lacquer are not attacked upon application of the further lacquer. This tempering occurs at temperatures of 180.degree. C. and partly leads to a modification of the shape of the lacquer supporting locations due to flowing. The planarization is deteriorated as a result thereof.
Y. Matsubara et al., IEDM Tech. Digest, p. 665 (1993) has proposed a further method for planarizing multi-layer metal wirings wherein strip-shaped supporting structures of photoresist are formed on an insulating layer that covers a metallization level. By targeted exposure in regions in which the metallization level exhibits few lines, the strip-shaped supporting structures are formed mainly in these regions. A second lacquer layer is applied and planarized in surface-wide fashion above the supporting structures.